Semiconductor memories are binary data memories in which a plurality of memory cells are provided. The memory cells are addressable by means of wordlines and bitlines. The main memory comprises a matrix of many memory cells connected to address decoding means and sense amplifiers. Addressing a memory cell, i.e. the selection of a memory cell, is performed by activating wordlines which are connected to address decoding means. The data stored in the addressed memory cells are read out by input/output units having sense amplifiers for amplifying the read-out data signal. The input/output units are connected to a data bus by means of which data can be read out from the memory or written into the memory.
When a random access memory is produced, it can happen that some of the memory cells within the matrix are faulty. Accordingly, the produced memory chip is tested, and it is decided whether it can be repaired. For this purpose, there is normally provided an on-chip circuitry to provide testing of the memory chip. The built-in self-test (BIST) is essentially the implementation of logic built into the memory chip to do testing without the use of a tester for data pattern generation on comparison purposes.
FIG. 1 shows the architecture of a memory chip according to the state of the art. The memory chip comprises a main memory with a plurality of memory cells and a redundancy logic having a built-in self-test device. The memory chip is connected to an address bus, a control bus and a data bus. In a test mode, the addresses of the faulty memory cells are detected. The redundancy logic replaces the faulty memory cells within the main memory with memory cells in the form of redundant registers within the redundancy logic. For this purpose the redundancy logic programs fuses within a fusebox. The address applied to the address bus is compared with the addresses of the detected faulty memory cells, and when there is a match, the redundancy logic maps the faulty address to an address of a register cell within the redundancy logic to replace the faulty memory cell. When reading data from the memory chip, the redundancy logic controls a multiplexer connected to the data bus. When accessing data with an address of a faulty memory cell, the data is read from the register replacing the memory cell within the redundancy logic.
FIG. 2 shows the architecture of a main memory within the memory chip according to the state of the art. In this example, the main memory is a 8k×16 wide memory having 16 input/output units and wordline address decoders (XDEC) for decoding the wordline address or X-address of the memory cells. The input/output units are connected to the memory cell matrix by means of vertical bitlines. The input/output units receive the bitline address or Y-address of the selected memory cell.
The main memory shown in FIG. 2 according to the state of the art is partitioned in two memory halves wherein the X-address decoders are placed in the center. With this architecture, the length of the wordlines is comparatively short so that the parasitic capacitance of the wordlines can be minimized. Each input/output unit is connected to the 16 bitlines for reading data from the addressed memory cell and for writing data into an addressed memory cell.
FIG. 3 shows the architecture of an input/output unit according to the state of the art. For reading out data, the input/output unit comprises multiplexer which are connected to the bitlines of the memory cell matrix. In the shown example, each memory cell is connected to a multiplexer via a couple or pair of bitlines BL, {overscore (BL)} to provide a differential signal to the input of the multiplexer. In the shown example, each multiplexer has N signal inputs. On the output side, each multiplexer is connected to a differential amplifier and an inverter for amplifying the read-out data signal and to supply the data to a data bus. The multiplexers are controlled by the applied Y-address. Each input output unit (IO) comprises a column decoder and a read/write amplifier.
In a conventional memory, there are provided either redundant registers, redundant bitlines and/or wordlines to repair a memory chip in case that faulty memory cells are detected when testing the memory chip.
If the conventional memory chip comprises redundant registers, the number of faulty addresses is limited by the number of redundant registers provided within the redundancy logic. If there are, for instance, ten redundant registers, it is only possible to repair ten faulty addresses. When an address is “faulty”, the address is stored in a redundant register. Since the number of faulty addresses detected by the main memory, it is not known before testing a considerable number of registers have to be provided within the redundancy logic to guarantee the repair of the chip even when a lot of memory cells are detected to be faulty.
In case that the memory chip comprises redundant bitlines BL and/or wordlines WL, the repair method is much more complex, because all errors have to be known in advance before the error pattern can be diagnosed and an optimal repair solution can be calculated. Storing detected memories with a conventional method implies a very large array.
Such an array needs a lot of space on the memory chip, thus increasing costs when producing the memory chip.
In European patent application EP 02022312.9 filed on Oct. 7, 2002 a method for storing detected errors in a separate diagnose array having a minimum storage and a memory chip having a diagnose array with a minimum storage size for storing detected errors of a main memory within the memory chip are described.
As can be seen from FIG. 4, the memory chip as described in EP 02022312.9 comprises a memory with a built-in redundancy. The memory comprises a plurality of memory cells which are addressable by means of wordlines and bitlines. The memory comprises redundant wordlines and redundant bitlines which are provided for repairing faulty memory cells. The memory is connected to a control block, a BIST-unit and a repair unit. The repair unit is connected to programmable fuses which are provided for replacing wordlines by redundant wordlines and input/output units by redundant input/output units within the memory.
The built-in self-test unit performs a test of the memory within the chip and checks whether there are any memory cells which are defective. The diagnose unit consists of a control unit and a diagnose array. The diagnose array is provided for storing logically detected errors within the main memory found by the built-in self-test device in a test mode. The diagnose array stores in a logical manner the errors found in the memory. The control unit controls the storing of detected errors into the diagnose array and analyzes the stored errors to select wordlines and input/output units within the memory to be replaced by redundant wordlines and redundant input/output units. Depending on the analyzing result, the repair unit programs fuses in a fusebox connected to the main memory. A basis of the data content of the storage table within the diagnose array, the repair unit performs a pre-fuse of the fuses to replace wordlines in the input/output unit of faulty memory cells by redundant wordlines and redundant input/output units. In the next step, the provisionally repaired memory is again tested, and if no further errors are detected, the fuses in the fusebox are blown.
FIG. 5 shows a memory array within a memory chip as shown in FIG. 4. The memory is partitioned in two memory halves A, B, each having a matrix of memory cells. The memory cells are connected to x-address-decoders (XDEC) and to input/output units I/O. The input/output units are connected to data input/output pads of the memory chip. Each input/output unit I/O is for example connected to 16 bitlines of the memory cell array.
As can be seen from FIG. 5, the memory further comprises redundant X-address decoders XDEC and redundant input/output units I/O red. Further, a control and comparator unit is provided connected to the address bus and to the fusebox via control lines.
FIG. 6 shows the architecture of the input/output units I/O in the memory chip as described in EP 02022312.9. As can be seen from FIG. 6, there is provided a redundant input/output unit I/O which may be activated by the programmed fuses. The fusebox is connected via control lines to multiplexers MUX A, B, C within a multiplex stage. The fusebox comprises the information data on the input/output unit I/O to be replaced by the redundant input/output unit I/O. A control signal is supplied to the multiplexer stage to block the input/output I/O which is connected to a faulty memory cell within the memory and which is decided to be replaced from the corresponding data pad The redundant input/output unit I/OR is connected to data pad C as a substitute. The redundant input/output unit I/OR is activated by the fuses. Providing the additional multiplexer stage has almost no impact on the signal delay.
As shown in FIG. 6 the memory chip comprises a memory cell array with several memory columns. Each column comprises eight to sixteen bitlines BL which are connected to a two stage multiplexer unit. FIG. 7 shows the structure of a two stage multiplexer unit in more detail. The memory column comprising for instance 16 bitlines BL is connected to the first stage of multiplexers each having four inputs. The output terminals of the multiplexers are connected to a further multiplexer having four inputs and one output. The four multiplexers of the first stage are controlled by a predecoding signal switching one of the four inputs to the second multiplexer stage in response to a predecoding control signal generated by a column decoder. The multiplexer of the second stage of the two stage multiplexer unit is controlled by a postdecoding control signal generated by the column decoder. The first stage of the two stage multiplexer unit comprises four multiplexers which preselect the data coming from the memory cells. The second stage of the multiplexer unit is provided for postdecoding having another multiplexer including a latch for the output data.
The predecoding and postdecoding signal is generated by the column decoder on the basis on an applied y-address. To this end the column decoder is connected to the address bus and receives the y-address.
The output of the two stage multiplexer unit is connected to sense amplifier for amplifying the bitline signal. The amplified signal is applied to a first input of a multiplexer which is provided for shifting a complete memory column having sixteen bitlines to another data output in case that it is detected that one memory column has at least one faulty bitline.
The shift stage comprises several multiplexers each having two inputs and one output. The multiplexers of the shift stage are controlled by a fuse data signal applied from a fuse box including programmable fuses. If it is detected that the memory column comprises at least one bitline which is faulty the fuses within the fuse box are programmed or blown to repair the memory cell array.
For example if it is detected that the memory column B as shown in FIG. 7 comprises a faulty bitline the output of the multiplexer unit B is blocked from the output data pad B by switching the multiplexer A of the shift stage to the first input being connected to the multiplexer unit A and switching multiplexer B of the shift stage to the output of the multiplexer unit C belonging to the adjacent memory column C. The memory column A is then switched to the next adjacent memory column and so on until a redundant memory column provided within the memory cell array is reached.
A disadvantage of the structure as shown in FIG. 7 is that only one bitline BL within a memory column is detected a complete memory column is blocked and shifted to the output data path of the adjacent memory column. According to repair only one bitline failure it is accordingly necessary to provide a complete redundant memory column which comprises sixteen bitlines. The provision of a redundant memory column having sixteen bitlines occupies a lot of area on the chip thus increasing production costs.
Accordingly it is the object of the invention to provide a repair circuit which needs a minimum area on the chip but which nevertheless repairs bitline failure reliably.